initial commit

4 years ago · ab6214e390
commit ab6214e390
16 changed files with 1372 additions and 0 deletions
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@ -0,0 +1,10 @@
+{
+    "spellright.language": [
+        "en_US"
+    ],
+    "spellright.documentTypes": [
+        "markdown",
+        "latex",
+        "plaintext"
+    ]
+}
--- a/architecture/isa.md
+++ b/architecture/isa.md
@ -0,0 +1,67 @@
+
+# Tritium-9 Instruction Set Architecture
+
+## Basic information
+| feature        | description |
+|----------------|-------------|
+|word size       |   9 trits   |
+|data bus size   |   9 trits   |
+|address bus size|   9 trits   |
+
+## Instruction types
+
+|        type        |   0   |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |
+|--------------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
+|(R)register/register|opcode |   _   |   _   | rdest |   _   | rsrc  |   _   | rsrc2 |   _   |  fn   |
+|(I)immediate        |opcode |   _   |   _   | rdest |   _   |  imm  |   _   |   _   |   _   |   _   |
+|(J)jump             |opcode |   _   |   _   | rdest |   _   | rcond |   _   |[empty]|   _   |  fn   |
+
+## Ternary values and representation
+
+| value | representation |
+|-------|----------------|
+|  -1   |       i        |
+|   0   |       0        |
+|   1   |       1        |
+
+## Registers 
+
+| name | address |
+|------|---------|
+|  r0  |   ii    |
+|  r1  |   i0    |
+|  r2  |   i1    |
+|  r3  |   0i    |
+|  r4  |   00    |
+|  r5  |   01    |
+|  r6  |   1i    |
+|  r7  |   10    |
+|  r8  |   11    |
+
+## Instructions
+
+| instruction | opcode | type | description |
+|-------------|--------|------|-------------|
+| nop         |  000   |  no  |does nothing |
+| ldi         |  00i   |  I   |loads immediate to `rdest`|
+| sti         |  001   |  I   |stores immediate to memory address `rdest`|
+| ld          |  0ii   |  R   |copies value at memory address `rsrc` to `rdest`|
+| st          |  0i0   |  R   |stores value from `rsrc` to memory address `rdest`|
+| [alu]       |  111   |  R   |runs an alu function setting `rdest` with the result of `fn(rsrc,rsrc2)`|
+| [jump]      |  iii   |  J   |runs a jump function to jump to `rdest` if `fn(rsrc)` is true|
+
+### ALU instructions
+
+| instruction | alu fn | description |
+|-------------|--------|-------------|
+| add         |   i    |adds `rsrc` to `rsrc2`|
+| sub         |   0    |subtracts `rsrc` from `rsrc2`|
+| cmp         |   1    |compares `rsrc2` to `rsrc2`, i if less than, 0 if equal, 1 if greater|
+
+### Jump instructions
+
+| instruction | jump fn | description |
+|-------------|---------|-------------|
+| blz         |    i    |jumps if `rcond` is less than zero|
+| bz          |    0    |jumps if `rcond` is zero|
+| bgz         |    1    |jumps if `rcond` is greater than zero|
--- a/21
+++ b/21
@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2020 Mikhail Licas/Schneide
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
--- a/materials.md
+++ b/materials.md
@ -0,0 +1,10 @@
+
+N Channel Enchantment - 2N7002
+P Channel Enchantment - BSS84
+N Channel Depletion   - BSS159 - Being phased out due to cost and rarity
+
+CMOS Complement - CD4007UBM - Being phased out due to cost
+
+Memory - 2x IS62WV25616BLL
+
+98 pin ISA connectors for backplane
--- a/readme.md
+++ b/readme.md
@ -0,0 +1,11 @@
+# Tritium Project
+An open source RISC based balanced ternary computer
+
+## What does balanced ternary mean?
+Normal computers process data in binary which means two states, a one and a zero. Ternary is similar except operating on three states. In balanced ternary, there is a negative (i), neutral (0), and positive (1) which means numbers are naturally signed thus simplifying the architecture and general logic. Ternary also has the best radix efficiency for any integer base of 1.0046 where binary is 1.0615 with base e 1.0000 being the most efficient. A 'trit' is the ternary analogue of a bit which stores an i,0, or 1. 
+
+## Has this been done before?
+There are many projects similar to this but they either haven't gone very far, closed source, or dead. The main inspiration for this computer is the Russian Setun computer, more specifically the Setun-70 which has an 18 trit word and 81 words of memory with a magnetic drum holding more memory. 
+
+## Variants
+9, 27, 54, and maybe even 81 trit word variants will be made with a similar architecture. The 9 trit architecture being dubbed 'Tritium-9' will be made first as an experiment and prototype.
--- a/simulation/binary_encoding/binary_encoding-cache.lib
+++ b/simulation/binary_encoding/binary_encoding-cache.lib
@ -0,0 +1,148 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Device_D
+#
+DEF Device_D D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "Device_D" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ TO-???*
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+P 2 0 1 10 -50 50 -50 -50 N
+P 2 0 1 0 50 0 -50 0 N
+P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R
+#
+DEF Device_R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "Device_R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Simulation_SPICE_VDC
+#
+DEF Simulation_SPICE_VDC V 0 1 N Y 1 F N
+F0 "V" 100 100 50 H V L CNN
+F1 "Simulation_SPICE_VDC" 100 0 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+F4 "Y" 0 0 50 H I L CNN "Spice_Netlist_Enabled"
+F5 "V" 0 0 50 H I L CNN "Spice_Primitive"
+F6 "dc(1)" 100 -100 50 H V L CNN "Spice_Model"
+DRAW
+C 0 0 100 0 1 10 f
+T 0 0 75 50 0 0 0 + Normal 0 C C
+P 2 0 0 0 -50 10 50 10 N
+P 2 0 0 0 -30 -10 -50 -10 N
+P 2 0 0 0 10 -10 -10 -10 N
+P 2 0 0 0 50 -10 30 -10 N
+X ~ 1 0 200 100 D 50 50 1 1 P
+X ~ 2 0 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# power_+5V
+#
+DEF power_+5V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+5V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +5V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_-5V
+#
+DEF power_-5V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 100 50 H I C CNN
+F1 "power_-5V" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
+X -5V 1 0 0 0 U 50 50 0 0 W N
+ENDDRAW
+ENDDEF
+#
+# power_GND
+#
+DEF power_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pspice_MNMOS
+#
+DEF pspice_MNMOS M 0 0 Y Y 1 F N
+F0 "M" 300 50 50 H V L CNN
+F1 "pspice_MNMOS" 300 -50 50 H V L CNN
+F2 "" -25 0 50 H I C CNN
+F3 "" -25 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -50 -100 -50 100 N
+P 2 0 1 0 -25 -100 100 -100 N
+P 2 0 1 0 100 100 -25 100 N
+P 2 0 1 0 200 0 -25 0 N
+P 4 0 1 0 -25 0 50 25 50 -25 -25 0 F
+P 2 1 1 0 -25 -100 -25 100 N
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 150 R 50 50 1 1 I
+X S 3 100 -200 100 U 50 50 1 1 P
+X B 4 200 -200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pspice_MPMOS
+#
+DEF pspice_MPMOS M 0 0 Y Y 1 F N
+F0 "M" 300 50 50 H V L CNN
+F1 "pspice_MPMOS" 300 -50 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -50 100 -50 -100 N
+P 2 0 1 0 -25 -100 100 -100 N
+P 2 0 1 0 100 100 -25 100 N
+P 2 0 1 0 200 0 -25 0 N
+P 4 0 1 0 200 0 125 25 125 -25 200 0 F
+P 2 1 1 0 -25 -100 -25 100 N
+X D 1 100 -200 100 U 50 50 1 1 P
+X G 2 -200 0 150 R 50 50 1 1 I
+X S 3 100 200 100 D 50 50 1 1 P
+X B 4 200 200 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
--- a/simulation/binary_encoding/binary_encoding.kicad_pcb
+++ b/simulation/binary_encoding/binary_encoding.kicad_pcb
@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
--- a/simulation/binary_encoding/binary_encoding.pro
+++ b/simulation/binary_encoding/binary_encoding.pro
@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
--- a/simulation/binary_encoding/binary_encoding.sch
+++ b/simulation/binary_encoding/binary_encoding.sch
@ -0,0 +1,485 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L power:GND #PWR02
+U 1 1 5FC2B1D9
+P 4900 4550
+F 0 "#PWR02" H 4900 4300 50  0001 C CNN
+F 1 "GND" H 4905 4377 50  0000 C CNN
+F 2 "" H 4900 4550 50  0001 C CNN
+F 3 "" H 4900 4550 50  0001 C CNN
+	1    4900 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+5V #PWR01
+U 1 1 5FC2C488
+P 4900 3950
+F 0 "#PWR01" H 4900 3800 50  0001 C CNN
+F 1 "+5V" H 4915 4123 50  0000 C CNN
+F 2 "" H 4900 3950 50  0001 C CNN
+F 3 "" H 4900 3950 50  0001 C CNN
+	1    4900 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:-5V #PWR03
+U 1 1 5FC2D9A8
+P 5400 3950
+F 0 "#PWR03" H 5400 4050 50  0001 C CNN
+F 1 "-5V" H 5415 4123 50  0000 C CNN
+F 2 "" H 5400 3950 50  0001 C CNN
+F 3 "" H 5400 3950 50  0001 C CNN
+	1    5400 3950
+	1    0    0    -1  
+$EndComp
+Text GLabel 4450 3950 1    50   Input ~ 0
+Vin
+Wire Wire Line
+	5400 4350 5400 4550
+Wire Wire Line
+	5400 4550 4900 4550
+Wire Wire Line
+	4900 4350 4900 4550
+Connection ~ 4900 4550
+Wire Wire Line
+	4450 4350 4450 4550
+Wire Wire Line
+	4450 4550 4900 4550
+$Comp
+L pspice:MPMOS M1
+U 1 1 5FC303C2
+P 6500 1650
+F 0 "M1" H 6788 1696 50  0000 L CNN
+F 1 "MPMOS" H 6788 1605 50  0000 L CNN
+F 2 "" H 6500 1650 50  0001 C CNN
+F 3 "~" H 6500 1650 50  0001 C CNN
+F 4 "M" H 6500 1650 50  0001 C CNN "Spice_Primitive"
+F 5 "BSS84" H 6500 1650 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 6500 1650 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "mos.lib" H 6500 1650 50  0001 C CNN "Spice_Lib_File"
+	1    6500 1650
+	1    0    0    -1  
+$EndComp
+$Comp
+L pspice:MNMOS M2
+U 1 1 5FC31BAF
+P 6500 3100
+F 0 "M2" H 6788 3146 50  0000 L CNN
+F 1 "MNMOS" H 6788 3055 50  0000 L CNN
+F 2 "" H 6475 3100 50  0001 C CNN
+F 3 "~" H 6475 3100 50  0001 C CNN
+F 4 "M" H 6500 3100 50  0001 C CNN "Spice_Primitive"
+F 5 "2N7002" H 6500 3100 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 6500 3100 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "mos.lib" H 6500 3100 50  0001 C CNN "Spice_Lib_File"
+	1    6500 3100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6300 1650 6200 1650
+Wire Wire Line
+	6200 1650 6200 2400
+Wire Wire Line
+	6200 3100 6300 3100
+Wire Wire Line
+	6200 2400 6100 2400
+Connection ~ 6200 2400
+Wire Wire Line
+	6200 2400 6200 3100
+Text GLabel 6100 2400 0    50   Input ~ 0
+Vin
+Wire Wire Line
+	6600 1450 6600 1350
+Wire Wire Line
+	6600 1350 6700 1350
+Wire Wire Line
+	6700 1350 6700 1450
+Wire Wire Line
+	6600 1350 6600 1250
+Connection ~ 6600 1350
+Wire Wire Line
+	6600 3300 6600 3400
+Wire Wire Line
+	6600 3400 6700 3400
+Wire Wire Line
+	6700 3400 6700 3300
+Wire Wire Line
+	6600 3400 6600 3500
+Connection ~ 6600 3400
+$Comp
+L power:-5V #PWR05
+U 1 1 5FC367B6
+P 6600 3500
+F 0 "#PWR05" H 6600 3600 50  0001 C CNN
+F 1 "-5V" H 6615 3673 50  0000 C CNN
+F 2 "" H 6600 3500 50  0001 C CNN
+F 3 "" H 6600 3500 50  0001 C CNN
+	1    6600 3500
+	-1   0    0    1   
+$EndComp
+$Comp
+L power:+5V #PWR04
+U 1 1 5FC37B3C
+P 6600 1250
+F 0 "#PWR04" H 6600 1100 50  0001 C CNN
+F 1 "+5V" H 6615 1423 50  0000 C CNN
+F 2 "" H 6600 1250 50  0001 C CNN
+F 3 "" H 6600 1250 50  0001 C CNN
+	1    6600 1250
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5FC38D5F
+P 6600 2100
+F 0 "R1" H 6670 2146 50  0000 L CNN
+F 1 "12k" H 6670 2055 50  0000 L CNN
+F 2 "" V 6530 2100 50  0001 C CNN
+F 3 "~" H 6600 2100 50  0001 C CNN
+	1    6600 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R2
+U 1 1 5FC39FBC
+P 6600 2650
+F 0 "R2" H 6670 2696 50  0000 L CNN
+F 1 "12k" H 6670 2605 50  0000 L CNN
+F 2 "" V 6530 2650 50  0001 C CNN
+F 3 "~" H 6600 2650 50  0001 C CNN
+	1    6600 2650
+	1    0    0    -1  
+$EndComp
+Connection ~ 6200 3100
+Wire Wire Line
+	6600 2800 6600 2900
+Wire Wire Line
+	6600 1850 6600 1950
+Wire Wire Line
+	6600 2250 6600 2400
+$Comp
+L Device:D D2
+U 1 1 5FC4D4BD
+P 7000 2400
+F 0 "D2" H 7000 2617 50  0000 C CNN
+F 1 "D" H 7000 2526 50  0000 C CNN
+F 2 "" H 7000 2400 50  0001 C CNN
+F 3 "~" H 7000 2400 50  0001 C CNN
+F 4 "D " H 7000 2400 50  0001 C CNN "Spice_Primitive"
+F 5 "DIODE" H 7000 2400 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 7000 2400 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "diode.lib" H 7000 2400 50  0001 C CNN "Spice_Lib_File"
+	1    7000 2400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7150 2400 7250 2400
+Text GLabel 7250 2400 2    50   Output ~ 0
+Low
+Wire Wire Line
+	6850 2400 6600 2400
+Connection ~ 6600 2400
+Wire Wire Line
+	6600 2400 6600 2500
+Wire Wire Line
+	6200 3100 6200 4000
+Wire Wire Line
+	6200 4000 6850 4000
+Wire Wire Line
+	7150 4000 7250 4000
+$Comp
+L Device:D D1
+U 1 1 5FC4479F
+P 7000 4000
+F 0 "D1" H 7000 4217 50  0000 C CNN
+F 1 "D" H 7000 4126 50  0000 C CNN
+F 2 "" H 7000 4000 50  0001 C CNN
+F 3 "~" H 7000 4000 50  0001 C CNN
+F 4 "D " H 7000 4000 50  0001 C CNN "Spice_Primitive"
+F 5 "DIODE" H 7000 4000 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 7000 4000 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "diode.lib" H 7000 4000 50  0001 C CNN "Spice_Lib_File"
+	1    7000 4000
+	1    0    0    -1  
+$EndComp
+Text GLabel 7250 4000 2    50   Output ~ 0
+High
+Connection ~ 7150 4000
+$Comp
+L power:GND #PWR07
+U 1 1 5FC4797E
+P 7150 4300
+F 0 "#PWR07" H 7150 4050 50  0001 C CNN
+F 1 "GND" H 7155 4127 50  0000 C CNN
+F 2 "" H 7150 4300 50  0001 C CNN
+F 3 "" H 7150 4300 50  0001 C CNN
+	1    7150 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L Simulation_SPICE:VDC V1
+U 1 1 5FC27AD5
+P 4450 4150
+F 0 "V1" H 4580 4241 50  0000 L CNN
+F 1 "VDC" H 4580 4150 50  0000 L CNN
+F 2 "" H 4450 4150 50  0001 C CNN
+F 3 "~" H 4450 4150 50  0001 C CNN
+F 4 "Y" H 4450 4150 50  0001 L CNN "Spice_Netlist_Enabled"
+F 5 "V" H 4450 4150 50  0001 L CNN "Spice_Primitive"
+F 6 "dc(-5)" H 4580 4059 50  0000 L CNN "Spice_Model"
+	1    4450 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R4
+U 1 1 5FC46370
+P 7150 4150
+F 0 "R4" H 7220 4196 50  0000 L CNN
+F 1 "10M" H 7220 4105 50  0000 L CNN
+F 2 "" V 7080 4150 50  0001 C CNN
+F 3 "~" H 7150 4150 50  0001 C CNN
+	1    7150 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L Simulation_SPICE:VDC V2
+U 1 1 5FC2900A
+P 4900 4150
+F 0 "V2" H 5030 4241 50  0000 L CNN
+F 1 "VDC" H 5030 4150 50  0000 L CNN
+F 2 "" H 4900 4150 50  0001 C CNN
+F 3 "~" H 4900 4150 50  0001 C CNN
+F 4 "Y" H 4900 4150 50  0001 L CNN "Spice_Netlist_Enabled"
+F 5 "V" H 4900 4150 50  0001 L CNN "Spice_Primitive"
+F 6 "dc(5)" H 5030 4059 50  0000 L CNN "Spice_Model"
+	1    4900 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L Simulation_SPICE:VDC V3
+U 1 1 5FC2A2B7
+P 5400 4150
+F 0 "V3" H 5530 4241 50  0000 L CNN
+F 1 "VDC" H 5530 4150 50  0000 L CNN
+F 2 "" H 5400 4150 50  0001 C CNN
+F 3 "~" H 5400 4150 50  0001 C CNN
+F 4 "Y" H 5400 4150 50  0001 L CNN "Spice_Netlist_Enabled"
+F 5 "V" H 5400 4150 50  0001 L CNN "Spice_Primitive"
+F 6 "dc(-5)" H 5530 4059 50  0000 L CNN "Spice_Model"
+	1    5400 4150
+	1    0    0    -1  
+$EndComp
+Connection ~ 7150 2400
+$Comp
+L power:GND #PWR06
+U 1 1 5FC4D4CB
+P 7150 2700
+F 0 "#PWR06" H 7150 2450 50  0001 C CNN
+F 1 "GND" H 7155 2527 50  0000 C CNN
+F 2 "" H 7150 2700 50  0001 C CNN
+F 3 "" H 7150 2700 50  0001 C CNN
+	1    7150 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R3
+U 1 1 5FC4D4C5
+P 7150 2550
+F 0 "R3" H 7220 2596 50  0000 L CNN
+F 1 "10M" H 7220 2505 50  0000 L CNN
+F 2 "" V 7080 2550 50  0001 C CNN
+F 3 "~" H 7150 2550 50  0001 C CNN
+	1    7150 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R7
+U 1 1 5FC95196
+P 9950 4050
+F 0 "R7" H 10020 4096 50  0000 L CNN
+F 1 "10M" H 10020 4005 50  0000 L CNN
+F 2 "" V 9880 4050 50  0001 C CNN
+F 3 "~" H 9950 4050 50  0001 C CNN
+	1    9950 4050
+	1    0    0    -1  
+$EndComp
+Text GLabel 9950 3150 2    50   Input ~ 0
+Vout
+Wire Wire Line
+	9950 2300 9950 3900
+Wire Wire Line
+	8900 1550 8900 3000
+Wire Wire Line
+	8900 3900 9550 3900
+$Comp
+L Device:D D4
+U 1 1 5FC951A2
+P 9700 3900
+F 0 "D4" H 9700 4117 50  0000 C CNN
+F 1 "D" H 9700 4026 50  0000 C CNN
+F 2 "" H 9700 3900 50  0001 C CNN
+F 3 "~" H 9700 3900 50  0001 C CNN
+F 4 "D " H 9700 3900 50  0001 C CNN "Spice_Primitive"
+F 5 "DIODE" H 9700 3900 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 9700 3900 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "diode.lib" H 9700 3900 50  0001 C CNN "Spice_Lib_File"
+	1    9700 3900
+	1    0    0    -1  
+$EndComp
+Connection ~ 9950 3900
+Wire Wire Line
+	9850 3900 9950 3900
+Wire Wire Line
+	9300 2300 9300 2400
+Wire Wire Line
+	9550 2300 9300 2300
+Wire Wire Line
+	9850 2300 9950 2300
+$Comp
+L Device:D D3
+U 1 1 5FC95177
+P 9700 2300
+F 0 "D3" H 9700 2517 50  0000 C CNN
+F 1 "D" H 9700 2426 50  0000 C CNN
+F 2 "" H 9700 2300 50  0001 C CNN
+F 3 "~" H 9700 2300 50  0001 C CNN
+F 4 "D " H 9700 2300 50  0001 C CNN "Spice_Primitive"
+F 5 "DIODE" H 9700 2300 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 9700 2300 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "diode.lib" H 9700 2300 50  0001 C CNN "Spice_Lib_File"
+	1    9700 2300
+	-1   0    0    1   
+$EndComp
+Connection ~ 9300 2300
+Wire Wire Line
+	9300 2150 9300 2300
+Wire Wire Line
+	9300 1750 9300 1850
+Wire Wire Line
+	9300 2700 9300 2800
+$Comp
+L Device:R R6
+U 1 1 5FC95169
+P 9300 2550
+F 0 "R6" H 9370 2596 50  0000 L CNN
+F 1 "12k" H 9370 2505 50  0000 L CNN
+F 2 "" V 9230 2550 50  0001 C CNN
+F 3 "~" H 9300 2550 50  0001 C CNN
+	1    9300 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R5
+U 1 1 5FC95163
+P 9300 2000
+F 0 "R5" H 9370 2046 50  0000 L CNN
+F 1 "12k" H 9370 1955 50  0000 L CNN
+F 2 "" V 9230 2000 50  0001 C CNN
+F 3 "~" H 9300 2000 50  0001 C CNN
+	1    9300 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+5V #PWR08
+U 1 1 5FC9515D
+P 9300 1150
+F 0 "#PWR08" H 9300 1000 50  0001 C CNN
+F 1 "+5V" H 9315 1323 50  0000 C CNN
+F 2 "" H 9300 1150 50  0001 C CNN
+F 3 "" H 9300 1150 50  0001 C CNN
+	1    9300 1150
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:-5V #PWR09
+U 1 1 5FC95157
+P 9300 3400
+F 0 "#PWR09" H 9300 3500 50  0001 C CNN
+F 1 "-5V" H 9315 3573 50  0000 C CNN
+F 2 "" H 9300 3400 50  0001 C CNN
+F 3 "" H 9300 3400 50  0001 C CNN
+	1    9300 3400
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	9300 3300 9300 3400
+Wire Wire Line
+	9400 3300 9400 3200
+Wire Wire Line
+	9300 3300 9400 3300
+Connection ~ 9300 3300
+Wire Wire Line
+	9300 3200 9300 3300
+Wire Wire Line
+	9300 1250 9300 1150
+Wire Wire Line
+	9400 1250 9400 1350
+Wire Wire Line
+	9300 1250 9400 1250
+Connection ~ 9300 1250
+Wire Wire Line
+	9300 1350 9300 1250
+Wire Wire Line
+	8900 3000 9000 3000
+Wire Wire Line
+	9000 1550 8900 1550
+$Comp
+L pspice:MNMOS M4
+U 1 1 5FC95140
+P 9200 3000
+F 0 "M4" H 9488 3046 50  0000 L CNN
+F 1 "MNMOS" H 9488 2955 50  0000 L CNN
+F 2 "" H 9175 3000 50  0001 C CNN
+F 3 "~" H 9175 3000 50  0001 C CNN
+F 4 "M" H 9200 3000 50  0001 C CNN "Spice_Primitive"
+F 5 "2N7002" H 9200 3000 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 9200 3000 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "mos.lib" H 9200 3000 50  0001 C CNN "Spice_Lib_File"
+	1    9200 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L pspice:MPMOS M3
+U 1 1 5FC95136
+P 9200 1550
+F 0 "M3" H 9488 1596 50  0000 L CNN
+F 1 "MPMOS" H 9488 1505 50  0000 L CNN
+F 2 "" H 9200 1550 50  0001 C CNN
+F 3 "~" H 9200 1550 50  0001 C CNN
+F 4 "M" H 9200 1550 50  0001 C CNN "Spice_Primitive"
+F 5 "BSS84" H 9200 1550 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 9200 1550 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "mos.lib" H 9200 1550 50  0001 C CNN "Spice_Lib_File"
+	1    9200 1550
+	1    0    0    -1  
+$EndComp
+Text GLabel 8900 3900 0    50   Input ~ 0
+High
+$Comp
+L power:GND #PWR010
+U 1 1 5FC95190
+P 9950 4200
+F 0 "#PWR010" H 9950 3950 50  0001 C CNN
+F 1 "GND" H 9955 4027 50  0000 C CNN
+F 2 "" H 9950 4200 50  0001 C CNN
+F 3 "" H 9950 4200 50  0001 C CNN
+	1    9950 4200
+	1    0    0    -1  
+$EndComp
+Text GLabel 8900 2300 0    50   Input ~ 0
+Low
+$EndSCHEMATC
--- a/simulation/binary_encoding/binary_encoding.sch-bak
+++ b/simulation/binary_encoding/binary_encoding.sch-bak
@ -0,0 +1,485 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L power:GND #PWR02
+U 1 1 5FC2B1D9
+P 4900 4550
+F 0 "#PWR02" H 4900 4300 50  0001 C CNN
+F 1 "GND" H 4905 4377 50  0000 C CNN
+F 2 "" H 4900 4550 50  0001 C CNN
+F 3 "" H 4900 4550 50  0001 C CNN
+	1    4900 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+5V #PWR01
+U 1 1 5FC2C488
+P 4900 3950
+F 0 "#PWR01" H 4900 3800 50  0001 C CNN
+F 1 "+5V" H 4915 4123 50  0000 C CNN
+F 2 "" H 4900 3950 50  0001 C CNN
+F 3 "" H 4900 3950 50  0001 C CNN
+	1    4900 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:-5V #PWR03
+U 1 1 5FC2D9A8
+P 5400 3950
+F 0 "#PWR03" H 5400 4050 50  0001 C CNN
+F 1 "-5V" H 5415 4123 50  0000 C CNN
+F 2 "" H 5400 3950 50  0001 C CNN
+F 3 "" H 5400 3950 50  0001 C CNN
+	1    5400 3950
+	1    0    0    -1  
+$EndComp
+Text GLabel 4450 3950 1    50   Input ~ 0
+Vin
+Wire Wire Line
+	5400 4350 5400 4550
+Wire Wire Line
+	5400 4550 4900 4550
+Wire Wire Line
+	4900 4350 4900 4550
+Connection ~ 4900 4550
+Wire Wire Line
+	4450 4350 4450 4550
+Wire Wire Line
+	4450 4550 4900 4550
+$Comp
+L pspice:MPMOS M1
+U 1 1 5FC303C2
+P 6500 1650
+F 0 "M1" H 6788 1696 50  0000 L CNN
+F 1 "MPMOS" H 6788 1605 50  0000 L CNN
+F 2 "" H 6500 1650 50  0001 C CNN
+F 3 "~" H 6500 1650 50  0001 C CNN
+F 4 "M" H 6500 1650 50  0001 C CNN "Spice_Primitive"
+F 5 "BSS84" H 6500 1650 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 6500 1650 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "mos.lib" H 6500 1650 50  0001 C CNN "Spice_Lib_File"
+	1    6500 1650
+	1    0    0    -1  
+$EndComp
+$Comp
+L pspice:MNMOS M2
+U 1 1 5FC31BAF
+P 6500 3100
+F 0 "M2" H 6788 3146 50  0000 L CNN
+F 1 "MNMOS" H 6788 3055 50  0000 L CNN
+F 2 "" H 6475 3100 50  0001 C CNN
+F 3 "~" H 6475 3100 50  0001 C CNN
+F 4 "M" H 6500 3100 50  0001 C CNN "Spice_Primitive"
+F 5 "2N7002" H 6500 3100 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 6500 3100 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "mos.lib" H 6500 3100 50  0001 C CNN "Spice_Lib_File"
+	1    6500 3100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6300 1650 6200 1650
+Wire Wire Line
+	6200 1650 6200 2400
+Wire Wire Line
+	6200 3100 6300 3100
+Wire Wire Line
+	6200 2400 6100 2400
+Connection ~ 6200 2400
+Wire Wire Line
+	6200 2400 6200 3100
+Text GLabel 6100 2400 0    50   Input ~ 0
+Vin
+Wire Wire Line
+	6600 1450 6600 1350
+Wire Wire Line
+	6600 1350 6700 1350
+Wire Wire Line
+	6700 1350 6700 1450
+Wire Wire Line
+	6600 1350 6600 1250
+Connection ~ 6600 1350
+Wire Wire Line
+	6600 3300 6600 3400
+Wire Wire Line
+	6600 3400 6700 3400
+Wire Wire Line
+	6700 3400 6700 3300
+Wire Wire Line
+	6600 3400 6600 3500
+Connection ~ 6600 3400
+$Comp
+L power:-5V #PWR05
+U 1 1 5FC367B6
+P 6600 3500
+F 0 "#PWR05" H 6600 3600 50  0001 C CNN
+F 1 "-5V" H 6615 3673 50  0000 C CNN
+F 2 "" H 6600 3500 50  0001 C CNN
+F 3 "" H 6600 3500 50  0001 C CNN
+	1    6600 3500
+	-1   0    0    1   
+$EndComp
+$Comp
+L power:+5V #PWR04
+U 1 1 5FC37B3C
+P 6600 1250
+F 0 "#PWR04" H 6600 1100 50  0001 C CNN
+F 1 "+5V" H 6615 1423 50  0000 C CNN
+F 2 "" H 6600 1250 50  0001 C CNN
+F 3 "" H 6600 1250 50  0001 C CNN
+	1    6600 1250
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5FC38D5F
+P 6600 2100
+F 0 "R1" H 6670 2146 50  0000 L CNN
+F 1 "12k" H 6670 2055 50  0000 L CNN
+F 2 "" V 6530 2100 50  0001 C CNN
+F 3 "~" H 6600 2100 50  0001 C CNN
+	1    6600 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R2
+U 1 1 5FC39FBC
+P 6600 2650
+F 0 "R2" H 6670 2696 50  0000 L CNN
+F 1 "12k" H 6670 2605 50  0000 L CNN
+F 2 "" V 6530 2650 50  0001 C CNN
+F 3 "~" H 6600 2650 50  0001 C CNN
+	1    6600 2650
+	1    0    0    -1  
+$EndComp
+Connection ~ 6200 3100
+Wire Wire Line
+	6600 2800 6600 2900
+Wire Wire Line
+	6600 1850 6600 1950
+Wire Wire Line
+	6600 2250 6600 2400
+$Comp
+L Device:D D2
+U 1 1 5FC4D4BD
+P 7000 2400
+F 0 "D2" H 7000 2617 50  0000 C CNN
+F 1 "D" H 7000 2526 50  0000 C CNN
+F 2 "" H 7000 2400 50  0001 C CNN
+F 3 "~" H 7000 2400 50  0001 C CNN
+F 4 "D " H 7000 2400 50  0001 C CNN "Spice_Primitive"
+F 5 "DIODE" H 7000 2400 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 7000 2400 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "diode.lib" H 7000 2400 50  0001 C CNN "Spice_Lib_File"
+	1    7000 2400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7150 2400 7250 2400
+Text GLabel 7250 2400 2    50   Output ~ 0
+Low
+Wire Wire Line
+	6850 2400 6600 2400
+Connection ~ 6600 2400
+Wire Wire Line
+	6600 2400 6600 2500
+Wire Wire Line
+	6200 3100 6200 4000
+Wire Wire Line
+	6200 4000 6850 4000
+Wire Wire Line
+	7150 4000 7250 4000
+$Comp
+L Device:D D1
+U 1 1 5FC4479F
+P 7000 4000
+F 0 "D1" H 7000 4217 50  0000 C CNN
+F 1 "D" H 7000 4126 50  0000 C CNN
+F 2 "" H 7000 4000 50  0001 C CNN
+F 3 "~" H 7000 4000 50  0001 C CNN
+F 4 "D " H 7000 4000 50  0001 C CNN "Spice_Primitive"
+F 5 "DIODE" H 7000 4000 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 7000 4000 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "diode.lib" H 7000 4000 50  0001 C CNN "Spice_Lib_File"
+	1    7000 4000
+	1    0    0    -1  
+$EndComp
+Text GLabel 7250 4000 2    50   Output ~ 0
+High
+Connection ~ 7150 4000
+$Comp
+L power:GND #PWR07
+U 1 1 5FC4797E
+P 7150 4300
+F 0 "#PWR07" H 7150 4050 50  0001 C CNN
+F 1 "GND" H 7155 4127 50  0000 C CNN
+F 2 "" H 7150 4300 50  0001 C CNN
+F 3 "" H 7150 4300 50  0001 C CNN
+	1    7150 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L Simulation_SPICE:VDC V1
+U 1 1 5FC27AD5
+P 4450 4150
+F 0 "V1" H 4580 4241 50  0000 L CNN
+F 1 "VDC" H 4580 4150 50  0000 L CNN
+F 2 "" H 4450 4150 50  0001 C CNN
+F 3 "~" H 4450 4150 50  0001 C CNN
+F 4 "Y" H 4450 4150 50  0001 L CNN "Spice_Netlist_Enabled"
+F 5 "V" H 4450 4150 50  0001 L CNN "Spice_Primitive"
+F 6 "dc(-5)" H 4580 4059 50  0000 L CNN "Spice_Model"
+	1    4450 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R4
+U 1 1 5FC46370
+P 7150 4150
+F 0 "R4" H 7220 4196 50  0000 L CNN
+F 1 "10M" H 7220 4105 50  0000 L CNN
+F 2 "" V 7080 4150 50  0001 C CNN
+F 3 "~" H 7150 4150 50  0001 C CNN
+	1    7150 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L Simulation_SPICE:VDC V2
+U 1 1 5FC2900A
+P 4900 4150
+F 0 "V2" H 5030 4241 50  0000 L CNN
+F 1 "VDC" H 5030 4150 50  0000 L CNN
+F 2 "" H 4900 4150 50  0001 C CNN
+F 3 "~" H 4900 4150 50  0001 C CNN
+F 4 "Y" H 4900 4150 50  0001 L CNN "Spice_Netlist_Enabled"
+F 5 "V" H 4900 4150 50  0001 L CNN "Spice_Primitive"
+F 6 "dc(5)" H 5030 4059 50  0000 L CNN "Spice_Model"
+	1    4900 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L Simulation_SPICE:VDC V3
+U 1 1 5FC2A2B7
+P 5400 4150
+F 0 "V3" H 5530 4241 50  0000 L CNN
+F 1 "VDC" H 5530 4150 50  0000 L CNN
+F 2 "" H 5400 4150 50  0001 C CNN
+F 3 "~" H 5400 4150 50  0001 C CNN
+F 4 "Y" H 5400 4150 50  0001 L CNN "Spice_Netlist_Enabled"
+F 5 "V" H 5400 4150 50  0001 L CNN "Spice_Primitive"
+F 6 "dc(-5)" H 5530 4059 50  0000 L CNN "Spice_Model"
+	1    5400 4150
+	1    0    0    -1  
+$EndComp
+Connection ~ 7150 2400
+$Comp
+L power:GND #PWR06
+U 1 1 5FC4D4CB
+P 7150 2700
+F 0 "#PWR06" H 7150 2450 50  0001 C CNN
+F 1 "GND" H 7155 2527 50  0000 C CNN
+F 2 "" H 7150 2700 50  0001 C CNN
+F 3 "" H 7150 2700 50  0001 C CNN
+	1    7150 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R3
+U 1 1 5FC4D4C5
+P 7150 2550
+F 0 "R3" H 7220 2596 50  0000 L CNN
+F 1 "10M" H 7220 2505 50  0000 L CNN
+F 2 "" V 7080 2550 50  0001 C CNN
+F 3 "~" H 7150 2550 50  0001 C CNN
+	1    7150 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R7
+U 1 1 5FC95196
+P 9950 4050
+F 0 "R7" H 10020 4096 50  0000 L CNN
+F 1 "10M" H 10020 4005 50  0000 L CNN
+F 2 "" V 9880 4050 50  0001 C CNN
+F 3 "~" H 9950 4050 50  0001 C CNN
+	1    9950 4050
+	1    0    0    -1  
+$EndComp
+Text GLabel 9950 3150 2    50   Input ~ 0
+Vout
+Wire Wire Line
+	9950 2300 9950 3900
+Wire Wire Line
+	8900 1550 8900 3000
+Wire Wire Line
+	8900 3900 9550 3900
+$Comp
+L Device:D D4
+U 1 1 5FC951A2
+P 9700 3900
+F 0 "D4" H 9700 4117 50  0000 C CNN
+F 1 "D" H 9700 4026 50  0000 C CNN
+F 2 "" H 9700 3900 50  0001 C CNN
+F 3 "~" H 9700 3900 50  0001 C CNN
+F 4 "D " H 9700 3900 50  0001 C CNN "Spice_Primitive"
+F 5 "DIODE" H 9700 3900 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 9700 3900 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "diode.lib" H 9700 3900 50  0001 C CNN "Spice_Lib_File"
+	1    9700 3900
+	1    0    0    -1  
+$EndComp
+Connection ~ 9950 3900
+Wire Wire Line
+	9850 3900 9950 3900
+Wire Wire Line
+	9300 2300 9300 2400
+Wire Wire Line
+	9550 2300 9300 2300
+Wire Wire Line
+	9850 2300 9950 2300
+$Comp
+L Device:D D3
+U 1 1 5FC95177
+P 9700 2300
+F 0 "D3" H 9700 2517 50  0000 C CNN
+F 1 "D" H 9700 2426 50  0000 C CNN
+F 2 "" H 9700 2300 50  0001 C CNN
+F 3 "~" H 9700 2300 50  0001 C CNN
+F 4 "D " H 9700 2300 50  0001 C CNN "Spice_Primitive"
+F 5 "DIODE" H 9700 2300 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 9700 2300 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "diode.lib" H 9700 2300 50  0001 C CNN "Spice_Lib_File"
+	1    9700 2300
+	-1   0    0    1   
+$EndComp
+Connection ~ 9300 2300
+Wire Wire Line
+	9300 2150 9300 2300
+Wire Wire Line
+	9300 1750 9300 1850
+Wire Wire Line
+	9300 2700 9300 2800
+$Comp
+L Device:R R6
+U 1 1 5FC95169
+P 9300 2550
+F 0 "R6" H 9370 2596 50  0000 L CNN
+F 1 "12k" H 9370 2505 50  0000 L CNN
+F 2 "" V 9230 2550 50  0001 C CNN
+F 3 "~" H 9300 2550 50  0001 C CNN
+	1    9300 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R5
+U 1 1 5FC95163
+P 9300 2000
+F 0 "R5" H 9370 2046 50  0000 L CNN
+F 1 "12k" H 9370 1955 50  0000 L CNN
+F 2 "" V 9230 2000 50  0001 C CNN
+F 3 "~" H 9300 2000 50  0001 C CNN
+	1    9300 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+5V #PWR08
+U 1 1 5FC9515D
+P 9300 1150
+F 0 "#PWR08" H 9300 1000 50  0001 C CNN
+F 1 "+5V" H 9315 1323 50  0000 C CNN
+F 2 "" H 9300 1150 50  0001 C CNN
+F 3 "" H 9300 1150 50  0001 C CNN
+	1    9300 1150
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:-5V #PWR09
+U 1 1 5FC95157
+P 9300 3400
+F 0 "#PWR09" H 9300 3500 50  0001 C CNN
+F 1 "-5V" H 9315 3573 50  0000 C CNN
+F 2 "" H 9300 3400 50  0001 C CNN
+F 3 "" H 9300 3400 50  0001 C CNN
+	1    9300 3400
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	9300 3300 9300 3400
+Wire Wire Line
+	9400 3300 9400 3200
+Wire Wire Line
+	9300 3300 9400 3300
+Connection ~ 9300 3300
+Wire Wire Line
+	9300 3200 9300 3300
+Wire Wire Line
+	9300 1250 9300 1150
+Wire Wire Line
+	9400 1250 9400 1350
+Wire Wire Line
+	9300 1250 9400 1250
+Connection ~ 9300 1250
+Wire Wire Line
+	9300 1350 9300 1250
+Wire Wire Line
+	8900 3000 9000 3000
+Wire Wire Line
+	9000 1550 8900 1550
+$Comp
+L pspice:MNMOS M4
+U 1 1 5FC95140
+P 9200 3000
+F 0 "M4" H 9488 3046 50  0000 L CNN
+F 1 "MNMOS" H 9488 2955 50  0000 L CNN
+F 2 "" H 9175 3000 50  0001 C CNN
+F 3 "~" H 9175 3000 50  0001 C CNN
+F 4 "M" H 9200 3000 50  0001 C CNN "Spice_Primitive"
+F 5 "2N7002" H 9200 3000 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 9200 3000 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "mos.lib" H 9200 3000 50  0001 C CNN "Spice_Lib_File"
+	1    9200 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L pspice:MPMOS M3
+U 1 1 5FC95136
+P 9200 1550
+F 0 "M3" H 9488 1596 50  0000 L CNN
+F 1 "MPMOS" H 9488 1505 50  0000 L CNN
+F 2 "" H 9200 1550 50  0001 C CNN
+F 3 "~" H 9200 1550 50  0001 C CNN
+F 4 "M" H 9200 1550 50  0001 C CNN "Spice_Primitive"
+F 5 "BSS84" H 9200 1550 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 9200 1550 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "mos.lib" H 9200 1550 50  0001 C CNN "Spice_Lib_File"
+	1    9200 1550
+	1    0    0    -1  
+$EndComp
+Text GLabel 8900 3900 0    50   Input ~ 0
+High
+$Comp
+L power:GND #PWR010
+U 1 1 5FC95190
+P 9950 4200
+F 0 "#PWR010" H 9950 3950 50  0001 C CNN
+F 1 "GND" H 9955 4027 50  0000 C CNN
+F 2 "" H 9950 4200 50  0001 C CNN
+F 3 "" H 9950 4200 50  0001 C CNN
+	1    9950 4200
+	1    0    0    -1  
+$EndComp
+Text GLabel 8900 2300 0    50   Input ~ 0
+Low
+$EndSCHEMATC
--- a/simulation/binary_encoding/diode.lib
+++ b/simulation/binary_encoding/diode.lib
@ -0,0 +1 @@
+.model DIODE D 2 1
--- a/simulation/binary_encoding/mos.lib
+++ b/simulation/binary_encoding/mos.lib
@ -0,0 +1,2 @@
+.model 2N7002 VDMOS(Rg=3 Vto=1.6 Rd=0 Rs=.75 Rb=.14 Kp=.17 mtriode=1.25 Cgdmax=80p Cgdmin=12p Cgs=50p Cjo=50p Is=.04p mfg=Fairchild Vds=60 Ron=2 Qg=1.5n)
+.model BSS84 VDMOS(pchan Rg=3 Vto=-2.1 Rd=2.4 Rs=1.8 Rb=3 Kp=.2 Cgdmax=.04n Cgdmin=.001n Cgs=.02n Cjo=.01n Is=2p mfg=Philips Vds=-50 Ron=6000m Qg=1n)
--- a/tritium/Memory_RAM_2.lib
+++ b/tritium/Memory_RAM_2.lib
@ -0,0 +1,60 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# IS62WV25616BLL
+#
+DEF IS62WV25616BLL U 0 40 Y Y 1 F N
+F0 "U" -450 1250 50 H V C CNN
+F1 "IS62WV25616BLL" 700 1250 50 H V C CNN
+F2 "Package_SO:TSOP-II-44_10.16x18.41mm_P0.8mm" -300 1200 50 H I C CNN
+F3 "" -550 -50 50 H I C CNN
+DRAW
+S -500 1200 500 -1200 0 1 0 f
+X A4 1 -500 700 100 L 50 50 1 1 I
+X I/O3 10 500 800 100 R 50 50 1 1 B
+X Vdd 11 50 1200 100 U 50 50 1 1 W
+X GND 12 50 -1200 100 D 50 50 1 1 W
+X I/O4 13 500 700 100 R 50 50 1 1 B
+X I/O5 14 500 600 100 R 50 50 1 1 B
+X I/O6 15 500 500 100 R 50 50 1 1 B
+X I/O7 16 500 400 100 R 50 50 1 1 B
+X ~WE 17 -500 -900 100 L 50 50 1 1 I
+X A16 18 -500 -500 100 L 50 50 1 1 I
+X A15 19 -500 -400 100 L 50 50 1 1 I
+X A3 2 -500 800 100 L 50 50 1 1 I
+X A14 20 -500 -300 100 L 50 50 1 1 I
+X A13 21 -500 -200 100 L 50 50 1 1 I
+X A12 22 -500 -100 100 L 50 50 1 1 I
+X A17 23 -500 -600 100 L 50 50 1 1 I
+X A11 24 -500 0 100 L 50 50 1 1 I
+X A10 25 -500 100 100 L 50 50 1 1 I
+X A9 26 -500 200 100 L 50 50 1 1 I
+X A8 27 -500 300 100 L 50 50 1 1 I
+X NC 28 500 -1100 100 R 50 50 1 1 N
+X I/O8 29 500 300 100 R 50 50 1 1 B
+X A2 3 -500 900 100 L 50 50 1 1 I
+X I/O9 30 500 200 100 R 50 50 1 1 B
+X I/O10 31 500 100 100 R 50 50 1 1 B
+X I/O11 32 500 0 100 R 50 50 1 1 B
+X Vdd 33 -50 1200 100 U 50 50 1 1 W
+X GND 34 -50 -1200 100 D 50 50 1 1 W
+X I/O12 35 500 -100 100 R 50 50 1 1 B
+X I/O13 36 500 -200 100 R 50 50 1 1 B
+X I/O14 37 500 -300 100 R 50 50 1 1 B
+X I/O15 38 500 -400 100 R 50 50 1 1 B
+X ~LB 39 -500 -1000 100 L 50 50 1 1 I
+X A1 4 -500 1000 100 L 50 50 1 1 I
+X ~UB 40 -500 -1100 100 L 50 50 1 1 I
+X ~OE 41 -500 -800 100 L 50 50 1 1 I
+X A7 42 -500 400 100 L 50 50 1 1 I
+X A6 43 -500 500 100 L 50 50 1 1 I
+X A5 44 -500 600 100 L 50 50 1 1 I
+X A0 5 -500 1100 100 L 50 50 1 1 I
+X ~CS1(CE) 6 -500 -700 100 L 50 50 1 1 I
+X I/O0 7 500 1100 100 R 50 50 1 1 B
+X I/O1 8 500 1000 100 R 50 50 1 1 B
+X I/O2 9 500 900 100 R 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
--- a/tritium/tritium.kicad_pcb
+++ b/tritium/tritium.kicad_pcb
@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
--- a/tritium/tritium.pro
+++ b/tritium/tritium.pro
@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
--- a/tritium/tritium.sch
+++ b/tritium/tritium.sch
@ -0,0 +1,4 @@
+EESchema Schematic File Version 2
+EELAYER 25 0
+EELAYER END
+$EndSCHEMATC
				`@ -0,0 +1 @@`
				`(kicad_pcb (version 4) (host kicad "dummy file") )`